1. Field of the Invention
The present invention relates to a heterojunction bipolar transistor and the manufacturing method thereof. More particularly, this invention relates to a semiconductor integrated circuit in which the above heterojunction bipolar transistor is used.
2. Description of the Prior Art
Generally, a known heterojunction bipolar transistor can overcome the shortcomings encountered with a homojunction bipolar transistor formed of silicon. By way of example, the description is presented on a heterojunction bipolar transistor having an AlGaAs emitter, a GaAs base and a GaAs collector. According to this heterojunction bipolar transistor, the hole as the majority carrier in the base cannot be diffused into the emitter due to the energy barrier caused by a band gap difference (.DELTA.Eg) between the emitter and the base. As a result, the base current is decreased and the efficiency of the electron injection from the emitter to the base is increased. Thus, even if the base concentration is increased and the emitter concentration is decreased, it is possible to increase the current gain (.beta.=I.sub.c /I.sub.B). This means that a base resistance and the junction capacitance between the base and the emitter relating to the high operation speed can be reduced. Experimentally, it was proved that this heterojunction bipolar transistor can be operated at speed higher than that of the bipolar transistor formed of silicon.
FIG. 1 shows an example of a typical AlGaAs/GaAs planar heterojunction bipolar transistor made by employing the ion implantation technique and the metal burying technique. An example of a method of manufacturing this AlGaAs/GaAs planar heterojunction bipolar transistor with this structure will be described briefly as follows.
In FIG. 1, reference numeral 13 generally designates the AlGaAs/GaAs planar heterojunction bipolar transistor. On a semi-insulating GaAs substrate 1, there are epitaxially grown an n.sup.+ -GaAs layer which will become a collector electrode deriving layer 2, an n-GaAs layer which will become a collector region 3, a p-GaAs layer which will become a base region (intrinsic base region) 4, an n-AlGaAs layer which will become an emitter region 5 and an n.sup.- -GaAs layer and n.sup.+ -GaAs layer which will become a capping layer 6 in this order. Then, the n.sup.+ -GaAs capping layer 6 is etched away so as to leave the emitter region, and the ion implanation for Mg is carried out by using an SiO.sub.2 mask and an external base region 7 is formed by the annealing process. Then, the ion implantation for boron B or H.sup.+ is carried out to form an element separating region 8 and a base/collector separating region 9. Thereafter, a window is formed through an SiO.sub.2 layer 10 on the collector electrode forming region to form a trench (groove) 11 and a metal 12 is buried into the trench 11, thus the transistor 13 being formed. In FIG. 1, reference numeral 14 denotes a base electrode, 15 an emitter electrode and 16 a collector electrode, respectively.
Meanwhile, there is proposed a so-called collector top heterojunction bipolar transistor 17 in which its collector region is formed at its surface side as shown in FIG. 2. The process for manufacturing this collector top heterojunction bipolar transistor is substantially the same as that for the emitter top heterojunction bipolar transistor 13, except the sequential order of the epitaxial growth. In FIG. 2, like parts corresponding to those of FIG. 1 are marked with the same references. In FIG. 2, reference numeral 18 denotes an n.sup.+ -GaAs layer which will become an emitter electrode deriving layer, 5 an n-AlGaAs layer which will become an emitter region, 4 a p-GaAs layer which will become a base region, 3 an n-GaAs layer which will become a collector region, 19 an n.sup.+ -GaAs layer which will become a collector cap layer and 7 an external base region.
A switching time .tau.s of the heterojunction bipolar transistor is given by the following equation ##EQU1## where Rb represents the base resistance, Cc the capacitance between the base and the collector, R.sub.L the load resistance, C.sub.L the load capacitance and .tau.b the base transit time. Therefore, to reduce the switching time .tau.s, the base resistance Rb and the capacitance Cc between the base and the collector must be reduced. In general, since collector top heterojunction bipolar transistor is more advantageous in reducing the capacitance Cc than the emitter top heterojunection bipolar transistor, the former is considered to be capable of operating at speed higher than the latter. The reason for this is as follows. (i) Since the collector top heterojunction bipolar transistor is small in collector dimension, the collector to base junction capacitance is reduced. This advantage permits high speed operation of the bipolar transistor. Conversely, the emitter dimension thereof is increased so that the emitter to base capacitance is increased. Although this is not a merit of the collector top heterojunction bipolar transistor, since the contact between the emitter and the base is the heterojunction, the capacitance therebetween becomes smaller than that of the homojunction. Further, since the emitter concentration is small, the emitter junction capacitance can be reduced originally, causing no trouble. The collector top heterojunction bipolar transistor has much more advantages by reducing the collector capacitance and it can operate at higher operation speed according to the demonstrated simulation results. (ii) In regard to the circuitry, in the case of the ECL (emitter-coupled-logic), the emitters of some transistors are commonly coupled to form a gate so that the dimension of element can be reduced by making the n.sup.+ emitter layers common without isolation.
In the above-mentioned conventional heterojunction bipolar transistors, if the dimension of the device is made smaller, the capacitance at the periphery of the active region, that is, the capacitances at the peripheries between the collector and the external base and between the emitter and the external base are relatively increased. For example, in the collector top heterojunction bipolar transistor shown in FIG. 2, calculating the capacitance where the collector dimension is 1.times.1 .mu.m.sup.2, the intrinsic capacitance is small such that the emitter to base capacitance is Ceb.congruent.2.7 fF and that the collector to base capacitance Cbc.congruent.0.27 fF (4000 .ANG. assumes the thickness of the depletion layer). However, the extrinsic capacitance, that is, the capacitances Ceb' and Cbc' produced only at the peripheries are very large as expressed in Ceb'.congruent.3.2 fF and Cbc'.congruent.0.5 fF. Thus, it is desired that the heterojunction bipolar transistor is constructed so as to suppress the capacitance at the peripheral portion as the dimension of the device is reduced. In practice, silicon bipolar transistors are constructed in this way.
In the heterojunction bipolar transistor shown, for example, in FIG. 2, if the external capacitance is reduced, the base contact region is reduced so that the base contact resistance is increased, thus restricting the operation speed of the element.
In addition to the above mentioned defects, the conventional heterojunction bipolar transistor with the external base formed by the ion implantation has the following defects.
(a) The concentration of the external base region cannot be increased.
(b) By the diffusion of the injected impurity into the emitter region and the diffusion of the impurity in the intrinsic base region, upon annealing for activation, the junction position is displaced.
(c) As the dimension of device is reduced, the external capacitances at peripheries produced between the emitter and the external base and between the collector and the external base are relatively increased. Particularly, the collector capacitance at the periphery cannot be removed.
(d) To derive the collector (or emitter) electrode, the techniques for forming a deep trench and burying a metal must be adopted.
(e) The contact dimension between the base and the emitter cannot be increased without increasing the capacitance.
(f) Of the electrons injected from the emitter region to the intrinsic base region, the electron at the periphery is diffused into the external base region by the diffusing length (several micrometers) and recombined with the hole to become a base current, thus causing a so-called periphery effect. Thus, when the element is reduced in size, the current gain is lowered.
(g) There is a limit in reducing the intrinsic region.